Big versus Little: Who will trip?

Since the marginal cost of operating powerful monolithic single core systems has become prohibitive, horizontal scaling has become the de-facto method for expanding computational power and maintaining acceptable levels of energy efficiency. While horizontal scaling is now the accepted means, there is still a debate as to whether this should be done with ”big” or ”little” architectures. While this subject has typically been approached from the perspective of performance or power, we choose to analyze it in the light of reliability. In recent years reliability has joined performance and power as a first-order design constraint in microprocessor design. The sensitivity of microprocessors to voltage fluctuations is a major concern in designing efficient low-power, reliable microarchitectures. Voltage fluctuations beyond a certain threshold can cause timing errors and operational failures in processors, risking the reliability of systems. While this has traditionally been studied in the context of few-core systems, compounding effects may be experienced by larger parallel and distributed systems which have become the mainstream in desktop/server class computing. In this paper, we perform a detailed evaluation of the characteristics of voltage noise in large many-core systems, comparing the differences in future many-core out-oforder (OOO) and inorder configurations. We find that single out-of-order cores experience larger voltage variations when compared to inorder cores, but also have a clear advantage in terms of performance. Based on our evaluation using parsec benchmarks, we find that for processes that scale with the number of cores, a number of OOO cores may be replaced by a larger number of inorder cores to achieve the same powerefficiency and performance with improved reliability. Keywords-Reliability; Voltage Noise; Out-of-order cores; Inorder cores; Power Efficiency